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	[CS61C FA20] Lecture 11.1 - RISC-V Instruction Formats I: Intro (CS 61C Departmental) View
	[CS61C FA20] Lecture 11.2 - RISC-V Instruction Formats I: R-Format Layout (CS 61C Departmental) View
	[CS61C FA20] Lecture 11.3 - RISC-V Instruction Formats I: I-Format Layout (CS 61C Departmental) View
	[CS61C FA20] Lecture 12.2 - RISC-V Instruction Formats II: Upper Immediates (CS 61C Departmental) View
	[CS61C FA20] Lecture 10.2 - RISC-V Procedures: Register Conventions (CS 61C Departmental) View
	Bits of Architecture: RISC-V Instruction Formats (Nick) View
	[CS61C FA20] Lecture 07.1 - RISC-V Intro: RISC-V Assembly Language (CS 61C Departmental) View
	[CS61C FA20] Lecture 09.2 - RISC-V Decisions II: A Bit About Machine Program (CS 61C Departmental) View
	RISC V instruction format (RealTime Sync) View
	[CS61C FA20] Lecture 19.6 - Single-Cycle CPU Datapath II: Adding U-Types (CS 61C Departmental) View